Digital adder circuit

ABSTRACT

A digital adder circuit has a plurality of adders for adding binary numbers. A carry calculator calculates carry data to a higher bit on the basis of added results of the plurality of adders, and a carry corrector adds the carry data to the added results of the plurality of adders. An accumulator accumulates a plurality of binary numbers sequentially supplied thereto. The accumulator includes more than two adders of a plurality of bits, a delay register for delaying each of outputs and each of carry outputs of the adders by a predetermined time. The binary numbers sequentially supplied thereto and a delayed output of the delay register are sequentially added by the adders, and a carry corrector supplied with an accumulated result expressed as redundant by each of outputs of the adders corrects each of the outputs by each of the carry outputs to generate an accumulated added result having no redundancy. Thus, the digital adder circuit and the accumulator can perform calculations at high speed without substantially increasing the size of the circuit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to adding circuits and, moreparticularly, to an adding circuit for adding binary numbers and anaccumulator for adding binary numbers sequentially supplied thereto inan accumulation fashion wherein high speed addition and accumulation canbe executed without increasing the circuit scale thereof too much.

2. Description of the Prior Art

As an adding circuit for adding binary numbers (a_(n-1), . . . a₁, a₀)and (b_(n-1), . . . b₁, b₀) of n bits (n is an integer larger than 2) toprovide binary numbers (c_(n), . . . c₁, c₀) of (n+1) bits, the mostpopular adding circuit is formed of one half adder and (n-1) fulladders.

FIG. 1 shows an example of such prior-art adding circuit, wherein n=16.

As shown in FIG. 1, this adding circuit comprises a half adder 1 andfull adders 2. In this popular adding circuit, carry data of the halfadder of least significant bit (LSB) is gradually propagated to the fulladders of most significant bit (MSB) to first provide accuratecalculated results. Therefore, t assumes a calculation time of one fulladder. Then, the total calculation time T₁ for adding binary number of nbits is expressed by the following equation (1):

    T.sub.1 ≈n t                                       (1)

Accordingly, if n is increased too much, a lot of calculation time isrequired depending on the calculation purpose.

In order to realize the high speed addition, an adding circuit of carryselect adder system is proposed. FIG. 2 shows an example of thepreviously-proposed carry select adder type adding circuit in whichn=16, by way of example.

As shown in FIG. 2, carry look ahead circuits 3A to 3D of 4 bits areconnected in cascade to calculate beforehand only carry data at highspeed. Adders 4A to 4D of 4 bits are provided to perform the additionassuming that carry data from less significant bits are "0", whereasadders 5B to 5D of 4 bits are provided to perform the addition assumingthat carry data from less significant bits are "1". Multiplexer circuits6B to 6D are employed as switching circuits.

The adder 4A adds 0'th to 3rd binary numbers (a₃. . . a₀ and b₃. . . b₀)of two binary numbers, the adder 4B adds binary numbers of 4th to 7thbits (a₇. . . a₄ and b₇. . . b₄) assuming that carry data from less than3 bits are "0", and the adder 5B adds binary numbers of 4th to 7th bitsassuming that the carry data from less than 3 bits are "1". By selectingthe added result of the adder 4B or 5B by using the multiplexer 6B inresponse to whether the carry data from the carry look ahead circuit 3Ais "0" or "1", the added result of binary numbers of 4th to 7th bits(c₇. . . c₄) can be obtained accurately. In the same fashion, addedresults (c₁₅ to c₈) of 8th to 15th bits of the binary numbers can beobtained accurately, and a value c₁₆ of 16th bit can be obtained ascarry data of the carry look ahead circuit 3D of the most significantbit.

Accordingly, a total calculation time required to perform the additionof binary numbers in the example of FIG. 2 becomes substantially equalto the calculation time of the 4-bit adder 4B or 5B. In the addingcircuit of the carry select adder system, assuming that the calculationtime of one carry look ahead circuit 3A, 3B and so on is selected to bet which is the calculation time of one 1-bit full adder and that k carrylook ahead circuits, i.e., k m-bit adders are utilized, then a totalcalculation time T₂ required to add binary numbers of n (=km where m isan integer) bits is expressed as:

    T.sub.2 ≈kt (in the case of k≧m)            (2A)

    or

    T.sub.2 ≈mt (in the case of k<m)                   (2B)

It is to be appreciated from the foregoing equations (2A) and (2B) that,as compared with the case of the standard adding circuit (see equation(1)), this can perform the calculation at speed as high as m times to ktimes.

In the adding circuit of the carry select adder system, a circuit block7D assumes a circuit formed of, for example, the adding circuits 4D and5D and the multiplexer 6D. Then, an adding circuit which modifies thecircuit block 7D is proposed as shown in FIG. 3. The technical report(Vol. 89, No. 4, PP. 37 to 44) of the Institute of Electronics,Informations and Communication Engineers describes this type of addingcircuit.

Referring to FIG. 3, the 4-bit adding circuit 5D (see FIG. 2) for addingbinary numbers is replaced with an adding circuit 8D for adding 1 to abinary number of 4 bits. This adding circuit 8D is interposed betweenthe output port of the adder 4D and one input port of the multiplexer6D. In that case, the calculation time at the adder 8D is added so thata total calculation time T₃ is expressed as:

    T.sub.3 ≈kt (in the case of k≧2m)           (3A)

    or

    T.sub.3 ≈2mt (in the case of k<2m)                 (3B)

Although the calculation speed of the adding circuit of the carry selectadder type can be increased as described above, this adding circuitneeds the addition of the multiplexers 6B to 6D, which unavoidably makesthe circuit scale large.

Further, if the circuit block of the example shown in FIG. 3 isemployed, then the calculation speed is decreased to be substantiallyone half as compared with the original carry select adder type. In thatcase, however, the adding circuit 5D is replaced with the adding circuit8D, which provides a reduced circuit scale. Even this circuit needs themultiplexers 6B to 6D, and there remains the substantial disadvantagethat the circuit scale is very large.

FIG. 4 shows an arrangement of a prior-art accumulator whichaccumulatively adds (i.e., accumulates) numbers x (x_(n-1). . . x₁, x₀)of less than n bits sequentially supplied thereto to obtain a sum s(s_(n-1). . . s₁, s₀) of n bits.

With reference to FIG. 4, an n-bit adder 201 is constructed byconnecting a single 1-bit half adder 202₀ and (n-1) 1-bit full adders202₁ to 202_(n-1). Delay registers 203₀ to 203_(n-1) are shown to haveclear terminals CLR and clock terminals CK. Sum outputs of the adders202₀ to 202_(n-1) are respectively supplied to input terminals of theregisters 203₀ to 203_(n-1), data x₀ to x_(n-1) of respective carries ofnumbers x are respectively supplied to first input terminals of theadders 202₀ to 202_(n-1), and delayed outputs of the registers 203₀ to203_(n-1), are supplied to the other input terminals of the adders 202₀to 202_(n-1), respectively.

When the accumulative addition is carried out by the accumulator in theexample of FIG. 4, a reset signal R is supplied to the clear terminalsCLR of the registers 203₀ to 203_(n-1) to reset the output data of theseregisters 203₀ to 203_(n-1) to zero. Then, the number x supplied to then-nit adder 201 is updated at a predetermined cycle and a clock pulse φ1of this predetermined cycle is supplied to the clock terminals CK of theregisters 203₀ to 203_(n-1). Thus, the output of the n-bit adder 201provides data S₀ to S_(n-1) of respective carries of the sum s of nbits. In that case, the carry output from the n'th bit which is the mostsignificant bit of the n-bit adder 201 to the (n+1) bits can beneglected.

In the n-bit adder 201, however, the accurate sum output is not obtaineduntil the carry output of the half adder 202₀ propagates up to the fulladder 202_(n-1). There is then the substantial disadvantage that, whenthe value n is increased, then the calculation speed is decreased.Assuming that T is calculation time of the one 1-bit half adder or fulladder, a calculation time required by the accumulator of the exampleFIG. 4 to perform one calculation is expressed as nearly nT.

Japanese Patent Laid-Open Gazette No. 64-86271 describes anotheraccumulator wherein regardless of the increase of the value n, acalculation time thereof is always substantially equal to thecalculation time T of the single 1-bit full adder. Thispreviously-proposed accumulator cannot avoid such a disadvantage thatthe circuit scale thereof still remains large. Further, it is frequentlyobserved that the calculation speed is not always increased to theextent of the single 1-bit full adder.

OBJECTS AND SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide animproved adding circuit whose calculation speed is higher as comparedwith a conventional adding circuit.

More specifically, it is an object of the present invention to providean adding circuit which can make the calculation speed high and in whichthe circuit scale can be reduced as compared with a conventional carryselect adder type adding circuit.

It is another object of the present invention to provide an accumulatorin which an accumulative addition can be performed at a necessarycalculation speed dependent on the usage without increasing the circuitscale too much.

As a first aspect of the present invention, a digital adder circuit foradding binary numbers comprises a plurality of adders for adding thebinary numbers divided a predetermined bits each, a carry calculator forcalculating carry data to a higher bit of the predetermined bit on thebasis of added results of the plurality of adders, and a carry correctorfor adding the carry data to the added results of the plurality ofadders within the predetermined bits.

In accordance with a second aspect of the present invention, anaccumulator for accumulating a plurality of binary numbers sequentiallysupplied thereto comprises more than two adders of a plurality of bits,a delay register for delaying each of outputs and each of carry outputsof the more than two adders of the plurality of bits by a predeterminedtime, the binary numbers sequentially supplied thereto and a delayedoutput of the delay register being sequentially added by the more thantwo adders of the plurality of bits, and a carry corrector supplied withan accumulated result expressed as redundant by each of outputs of themore than two adders of the plurality of bits and carry outputs and forcorrecting each of the outputs by each of the carry outputs to generatean accumulated added result having no redundancy.

The preceding, and other objects, features and advantages of the presentinvention will be apparent in the following detailed description ofpreferred embodiments when read in conjunction with the accompanyingdrawings, in which like reference numerals are used to identify the sameor similar parts in the several views.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing an example of a standardadding circuit of the prior art;

FIG. 2 is a schematic block diagram showing a prior-art adding circuitof a carry select adder system;

FIG. 3 is a schematic block diagram showing a modified example of theconventional carry select adder system adding circuit shown, in FIG. 2;

FIG. 4 is a schematic block diagram showing an example of a conventionalaccumulator;

FIG. 5 is a block diagram showing a first embodiment of an addingcircuit according to the present invention;

FIG. 6 is a schematic block diagram showing a main portion of the addingcircuit of FIG. 5;

FIG. 7 is a schematic block diagram showing another example of the mainportion of the adding circuit shown in FIG. 5;

FIG. 8 is a schematic diagram used to explain an operation of the addingcircuit of FIG. 5;

FIG. 9 is a schematic block diagram showing a second embodiment of theadding circuit according to the present invention;

FIG. 10 is a schematic block diagram showing an embodiment of theaccumulator according to the present invention;

FIGS. 11A, 11B, 11C, 11D and 11E are schematic representations used toexplain an operation of the embodiment shown in FIG. 10; and

FIG. 12 is a schematic block diagram showing another embodiment of theaccumulator which is provided by generalizing the accumulator of thepresent invention shown in FIG. 10.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

An embodiment of an adding circuit according to the present inventionwill be described with reference to FIGS. 5 to 8. In this embodiment,the present invention is applied to an adding circuit which obtains abinary number (c₁₆, c₁₅. . . c₀) of 17 bits by adding two binary numbers(a₁₆. . . a₀) and (b₁₅. . . b₀) of 16 bits.

FIG. 5 is a block diagram which shows the embodiment of the addingcircuit according to the present invention.

With reference to FIG. 5, 4-bit adders 9A to 9D are provided to add twobinary numbers of 4 bits. The binary numbers of 16 bits are divided toprovide binary numbers of 4 bits each and binary numbers (a₃. . . a₀)and (b₃. . . b₀) of least significant 4 bits are added by the adder 9A.The binary numbers (a₇. . . a₄) and (b₇. . . b₄) of the next 4 bits areadded by the adder 9B. The binary numbers (a₁₁. . . a₈) and (b₁₁. . .b₈) of the next 4 bits are added by the adder 9C. Finally, binarynumbers (a₁₅. . . a₁₂) and (b₁₅. . . b₁₂) of the most significant 4 bitsare added by the adder 9D. The added outputs of 4 bits excepting thecarry data of the adder 9A is provided as the least significant 4 bits(c₃. . . c₀) of the finally obtained added result, while carry data e₄,e₈, e₁₂, e₁₆ are generated from carry output terminals CA of the adders9A to 9D, respectively.

The carry data e₄ of the adder 9A and the added results (d₇ . . . d₄) of4 bits from the adder 9B are supplied to input terminals of 5-input ANDcircuit 10B, and output data of this AND circuit 10B and the carry datae₈ of the adder 9B are supplied to input terminals of an OR circuit 11B.Accurate carry data E₈ to the 8th bit (which will be described later),which is the output data of the OR circuit 11B, and added results (d₁₁.. . d₈) of 4 bits from the adder 9C are supplied to input terminals of a5-input AND circuit 10C. Output data of this AND circuit 10C and carrydata e₁₂ of the adder 9C are supplied to an OR circuit 11C. Accuratecarry data E₁₂ to the 12th bit, which is the output data from the ORcircuit 11C, and added results (d₁₅. . . d₁₂) of 4 bits from the adder9D are supplied to input terminals of a 5-input AND circuit 10D, andoutput data from the AND circuit 10D and carry data e₁₆ of the adder 9Dare supplied to input terminals of OR circuit 11D. Output data E₁₆ ofthis OR circuit 11D is provided as 16th bit value c₁₆ of the final addedresult. Therefore, the circuit groups (10B, 11B), (10C, 11C) and (10D,11D) can be regarded as carry computers (or calculators) 13B, 13C and13D, respectively.

As illustrated in FIG. 5, adders 12B to 12D are provided to add binarynumbers of 1 bit to binary numbers of 4 bits to obtain binary numbers of4 bits. These adders 12B to 12D are referred hereinafter as "A4 blocks"in the following description. These A4 blocks 12B to 12D do notcalculate carry data for 4th bit. The A4 block 12B adds the carry datae₄ to the added results (d₇ . . . d₄) of the adder 9B, the A4 block 12Cadds the accurate carry data E₈ to the added results (d₁₁ to d₈), andthe A4 block 12D adds the accurate carry data E₁₂ to the added results(d₁₅. . . d₁₂) of the adder 9D. The added results of 12 bits of these A4blocks 12B to 12D are obtained as 12-bit values (c₁₅. . . c₄) of thefinally added results.

FIG. 6 shows an example of the A4 block 12B (see FIG. 5).

Referring to FIG. 6, half adders 14A to 14D are provided, wherein anintermediate added result d₄ and carry data e₄ are supplied to differentinput terminals of the half adder 14A, respectively, intermediate addedresults d₅ to d₇ are supplied to first input terminals of the halfadders 14B to 14D, respectively, and carry data from the half adders14A, 14B and 14C are supplied to the other input terminals of the halfadders 14B, 14C and 14D, respectively. The added results of these halfadders 14A to 14D are obtained as final added results (c₇. . . c₄). Inthat case, assuming that a calculation time of one half adder isrepresented by t, a total calculation time required by the A4 block 12Bin the example of FIG. 6 to obtain an accurate value is substantially4t.

FIG. 7 shows another example of the A4 block 12B, in which referencenumerals 15A to 15D designate exclusive-OR circuits, 16 a 2-input ANDcircuit, 17 a 3-input AND circuit and 18 a 4-input AND circuit,respectively. As shown in FIG. 7, the intermediate added result d₄ andcarry data e₄ are supplied to different input terminals of theexclusive-OR circuit 15A, different input terminals of the AND circuit16, different input terminals of the AND circuit 17 and to differentinput terminals of the AND circuit 18. Output data of the AND circuit 16is supplied to one input terminal of the exclusive-OR circuit 15B, whilethe intermediate added result d₅ is supplied to the other input terminalof the exclusive-OR circuit 15B, a third input terminal of the ANDcircuit 17 and to a third input terminal of the AND circuit 18. Further,output data from the AND circuit 17 is supplied to one input terminal ofthe exclusive-OR circuit 15C, and the intermediate added result d₅ issupplied to the other input terminal of the exclusive-OR circuit 15C andto a fourth input terminal of the AND circuit 18. Output data from theAND circuit 18 and the intermediate added result d₇ are supplied todifferent input terminals of the exclusive-OR circuit 15D, respectively.Output data from these exclusive-OR circuits 15A to 15D are obtained asfinal added results (c₇ to c₄).

The addition in which binary numbers (d₇. . . d₄) of 4 bits can be addedwith the carry data e₄ of one bit in the example of FIG. 7 will bedescribed in detail.

Only when (d₄, e₄)=(1, 0) or (d₄, e₄)=(0, 1), the value c₄ becomes "1"so that the output data of the exclusive-OR circuit 15A becomes thevalue C₄, accurately. Further, assuming that f₁ represents carry datafrom 0'th bit to 1st bit then f₁ becomes "1" only when (d₄, e₄)=(1, 1),while the value c₅ becomes "1" only when (d₅, f₁)=(1, 0) or (d₅, f₁)=(0,1). Thus, the output data from the exclusive-OR circuit 15B takes thevalue c₅, accurately. Similarly, assuming that f₂ represents carry datato the 2nd bit and that f₃ represents carry data to the 3rd bit, then f₂becomes "1" only when (d₅, d₄, e₄)=(1, 1, 1) and f₃ becomes "1" onlywhen (d₆, d₅, d₄, e₄)=(1, 1, 1, 1). Therefore, the output data from theexclusive-OR circuits 15C and 15D, respectively take values c₆ and c₇,accurately.

The example of FIG. 7 shows the circuit which performs the addition in aso-called table fashion. According to this circuit arrangement, thetotal calculation time can be reduced to about a calculation time of onefull adder.

While in the above-mentioned example, the carry data to the 8th, 12thand 16th are not calculated in the respective A4 blocks 12B, 12C and12D, these carry data are calculated by the carry computers (orcalculator) 13B, 13C and 13D, respectively. A calculation in whichaccurate carry data E₈ to the 8th bit is obtained by the carry computer13B will be described first.

The carry data E₈ becomes "1" only when carry data e₈ of 4-bit adder 9Bis "1" or when carry data e₄ of the less significant 4-bit adder 9A andthe added result (d₇. . . d₄) of the adder 9B suffice (d₇, d₆, d₅, d₄,e₄)=(1, 1, 1, 1, 1). Accordingly, the carry computer 13B, formed by thecombination of the 5-input AND circuit 10B and the OR circuit 11B, canderive accurate carry data E₈ to the 8th bit.

Further, the accurate carry data E₁₂ to the 12th bit becomes "1" onlywhen carry data e₁₂ of the adder 9C is "1" or when carry data E₈ to 8thbit and added result (d₁₁. . . d₈) of the adder 9C suffice (d₁₁, d₁₈,d₉, E₈)=(1, 1, 1, 1, 1). Therefore, accurate carry data E₁₂ to 12th bitcan be obtained by the carry computer 13C which is formed by thecombination of the 5-input AND circuit 10C and the OR circuit 11C.Similarly, accurate carry data E₁₆ to 16th bit can be obtained by thecarry computer 13D which is formed by the combination of the 5-input ANDcircuit 10D and the OR circuit 11D.

An operation in which two binary numbers can be added in the example ofFIG. 5 will be summarized with reference to FIG. 8. Initially, twobinary numbers are divided into 4 sections of 4 bits and additions areperformed for these 4 sections of 4 bits in steps 101 to 104. Then,carry data e₄ obtained in step 101 directly becomes accurate carry datato 4th bit (at step 105), and accurate carry data E₈ to 8th bit iscalculated (in step 106) from the carry data e₄ and added result of 4bits obtained in step 102. Accurate carry data E₁₂ to 12th bit iscalculated (in step 107) from the carry data E₈ and added result of 4bits obtained in step 103, and accurate carry data E₁₆ to 16th bit isobtained (in step 108) from the carry data E₁₂ and added result of 4bits obtained at step 104.

Finally, the least significant 4 bits of the added result in step 101directly become the least significant 4 bits (c₃. . . c₀) of addedresult finally obtained (in step 109). Then, data of 4 bits (c₇ . . .c₄) is obtained (in step 110) by adding the carry data e₄ to the 4 bitsof the added result at step 102. Data of 4 bits (c₁₁. . . c₈) areobtained (in step 111) by adding the carry data E₈ to less significant 4bits of the added result in step 103, and data of 4 bits (c₁₅. . . c₁₂)are obtained (in step 112) by adding the carry data E₁₂ to 4 bits of theadded result in step 104. The carry data E₁₆ becomes data c₁₆ which isfinally provided as the most significant bit (MSB) (in step 113).

Let us now evaluate a total calculation time T_(x) of the example shownin FIG. 5, in which two input data assume binary numbers of n bits andthe addition is performed under the condition that these input data aredivided by m bits each. That is, n=km (k is an integer) is establishedand the adders 9A to 9D are replaced with k m-bit adders. In that case,the calculation times of the carry computers 13B, 13C and the like areapproximately the same as the calculation time t of one 1-bit full adderso that, when a circuit similar to that of the example of FIG. 7 isemployed as the A4 blocks 12B, 12C or the like, the calculation times ofthe A4 blocks 12B, 12C or the like become substantially t. Thus, thetotal calculation time T_(x) is expressed as:

    T.sub.x ≈}m+(k-2)+1}t=(m+k-1)t                     (4)

Thus, the total calculation time T_(x) in this example can beconsiderably reduced as compared with the total calculation time T₁(equation (1)) of the prior-art example shown in FIG. 1. However, thiscalculation time T_(x) is slightly longer as compared with the totalcalculation time T₂ (equation (2A) or (2B)) of the carry select addersystem of the prior-art example shown in FIG. 2.

When the circuit in the example of FIG. 6 is employed as the A4 blocks12B, 12C or the like, the total calculation time T_(x) is provided as avalue which results from adding m t to the equation (4).

The circuit scale of a example of FIG. 5 is made smaller than that ofthe carry select adder system because the circuit shown in FIG. 5 doesnot employ the multiplexer. Further, while the carry computers 13B, 13Cand so on are supplied with only data of (m+1) bits, the carry lookahead circuits 3A, 3B and the like in the example of FIG. 2 are suppliedwith data of (2m+1) bits, the circuit scale of the carry computers 13B,13C and the like can be reduced to substantially 1/2 as compared withthat of the carry look ahead circuits 3A, 3B and the like. From thisstandpoint, there is then the advantage that the overall circuit scalecan be made small.

A second embodiment of the present invention will be described withreference to FIG. 9. In this embodiment, the present invention isapplied to an adding circuit which produces a binary number of 10 bits(c₉ , c₈. . . c₀) by adding two binary numbers of 9 bits (a₈. . . a₀)and (b₈. . . b₀).

In this embodiment, input data of 9 bits are divided to provide 4 bits,2 bits and 3 bits from the least significant bit (LSB).

In FIG. 9, reference numeral 19 designates a 4-bit adder, 20 a 2-bitadder and 21 a 3-bit adder, respectively. These adders 19, 20 and 21perform the additions of binary numbers which are divided into 4 bits, 2bits and 3 bits, respectively. Carry data e₄ of the adder 19 and anadded result of less significant 2 bits of the adder 20 are supplied todifferent input terminals of a 3-input AND circuit 22, respectively, andoutput data of this 3-input AND circuit 22 and carry data e₆ of theadder 20 are supplied to an OR circuit 24A, from which there is derivedaccurate carry data E₆ to the 6th bit. Then, accurate carry data E₉ tothe 9th bit is calculated from the carry data E₆, an added result ofless significant 3 bits of the adder 21 and carry data e₉ of the adder21.

Further, in FIG. 9, reference numeral 25 designates an adder (A2 block)which adds data e₄ of 1 bit to the binary numbers of 2 bits andreference numeral 26 designates an adder (A3 block) which adds data E₆of 1 bit to the binary numbers of 3 bits. An added result of lesssignificant 4 bits of the adder 19, an added result of 2 bits of the A2block 25 and an added result of 3 bits of the A3 block become finaladded results (c₈. . . c₀) and the carry data E₉ directly becomes avalue c₉ of final 9th bit. The operation and effects of the example ofFIG. 9 are the same as those of the example of FIG. 5 and therefore neednot be described.

A first embodiment of an accumulator which utilizes the adding circuitof the present invention will be described with reference to FIGS. 10and 11. In this embodiment, the present invention is applied to anaccumulator circuit which produces a sum s (s₈. . . S₁, S₀) of 9 bits byaccumulating numbers x (x₈. . . x₁, x₀) of less than 9 bits which aresequentially supplied thereto.

FIG. 10 shows an accumulator of this embodiment. Referring to FIG. 10,three 3-bit adders 204A to 204C are formed of three 1-bit full adders,delay registers 203₀ to 203₈ and 205A to 205B are provided, each ofwhich has clear and clock terminals, and data holding registers 206₀ to206₈ and 207A and 207B are provided, each of which has a clock terminal(each of these registers is represented by reference letter R in FIG. 10for simplicity). Further, there is shown a 6-bit adder 208 whichcomprises of six 1-bit full adders.

In this embodiment, 0 is supplied to carry input terminal CI of the3-bit adder 204A, and data x₀ (LSB) to x₂ of the least significant 3bits of the number x to be added are respectively supplied to firstinput terminals of the first bit input terminal b₀ to the third bitinput terminal b₂ of the 3-bit adder 204A. Sum output of 3 bitstherefrom are respectively supplied through the delay registers 203₀ to203₂ to the other input terminals of the first bit input terminal b₀ tothe third bit input terminal b₂ of the 3-bit adder 204A. A carry outputto 4th bit produced at the carry output terminal CO of the delayregister 204A is supplied through the delay register 205A to the carryinput terminal CI of the 3-bit adder 204B.

Data x₃ to x₅ of 3 bits of the number x to be added are respectivelysupplied to first input terminals of the first bit input terminal to thethird input terminal of the 3-bit adder 204B, and sum outputs of 3 bitstherefrom are respectively supplied through the delay registers 203₃ to203₅ to the other input terminals of the first bit input terminal to thethird bit input terminal. A carry output to 4th bit (7th bit as thenumbers x) is supplied through the delay register 205B to the carryinput terminal CI of the 3-bit adder 204C. Simultaneously, data of themost significant 3 bits x₆ to x₈ of the numbers x to be added arerespectively supplied to first input terminals of the first to the thirdinput terminals of the 3-bit adder 204C and sum outputs of 3 bitstherefrom are respectively supplied through the delay registers 203₆ to203₈ to the other input terminals of the first to third input terminalsof the 3-bit adder 204C, while its carry output terminal CO is opened.

Sum outputs of 3 bits from the 3-bit adder 204A are accumulated by thedata holding registers 206₀ to 206₂ and provided as the leastsignificant 3 bits s₀ to s₂ of the sum s. A carry output of the 3-bitadder 204A is supplied through the data holding register 207A to oneinput terminal of the first bit b₀ input terminal of the 6-bit adder 208and 0 is supplied to the carry input terminal CI and first inputterminals of the second bit b₁ and third bit b₂ input terminals of the6-bit adder 208. The sum outputs of 3 bits from the 3-bit adder 204B arerespectively supplied through the data holding registers 206₃ to 206₅ tothe other input terminals of the first bit b₀ to third bit b₂ inputterminals of the 6-bit adder 208. A carry output of the 3-bit adder 204Bis supplied through the data holding register 207B to one input terminalof the fourth bit b₃ input terminal of the 6-bit adder 208, and 0 issupplied to first input terminals of the fifth bit b₄ and sixth bit b₅input terminals of the 6-bit adder 208. Sum outputs of 3 bits from the3-bit adder 204C are respectively supplied through the data holdingregisters 206₆ to 206₈ to the other input terminals of the fourth bit b₃to sixth bit b₆ input terminals of the 6-bit adder 208, and a carryoutput terminal CO of the 6-bit adder 208 is opened. Sum outputs of 6bits from the 6-bit adder 208 become the most significant 6-bits S₃ toS₈ of the sum s which is the accumulated result.

An operation of this accumulator will be described with reference toFIGS. 11A to 11E. In that case, the numbers x to be sequentiallysupplied are represented as n numbers (n is an integer larger than 2) ofx₁ to x_(n) and the bit arrangement of the number x₁ (i=1 to n) isexpressed by (x_(n) 8 (MSB) to x_(n) 1, x_(n) 0 (LSB.). Further, thenumbers x₁ to x_(n) are sequentially supplied at a predetermined cycleand a cycle of a clock pulse φ₁ supplied to the delay registers 203₀ to203₈. 205A and 205B is made coincident with the former predeterminedcycle. Also, a clock pulse φ₂ supplied to the data holding registers206₀ to 206₈ and 207A and 207B occurs only when the sum s of the numbersx₁ to x_(n) is finally generated in the expression of ordinary 9 bits.

In this embodiment, 0 is set as delay outputs of the delay registers203₀ to 203₈, 205A and 205B by a reset pulse R for initialization andthe numbers x₁ (x₁₈. . . x₁₀) added during the first cycle are suppliedthereto. The resultant added results are the numbers x₁ (FIG. 11A),whereby the numbers x₁ are generated as the sum outputs of the 3-bitadders 204A to 204C and two carry outputs are both 0. When the clock φ₁is generated, the sum outputs and the carry outputs (i.e., accumulatedresults of the previous time) of the 3-bit adders 204A to 204C arerespectively fed through the delay registers 203₀ to 203₈, 205A and 205Bto the input sides of the 3-bit adders 204A to 204C and approximatelysimultaneously numbers x₂ (x₂₈. . . x₂₀) added during the second cycleare supplied to the input sides of the 3-bit adders 204A to 204C,whereby outputs (s₂₈. . . s₂₀), c₂₃ and c₂₆ are obtained as sum outputsof the 3-bit adders 204A to 204C, a carry output to the third bit and acarry output to the sixth bit.

The expression of the accumulated result of the sum outputs (s₂₈. . .s₂₀) and the carry outputs c₂₃ and c₂₆ is what might be called aredundancy expression. Since the above-mentioned redundancy expressionis employed in this embodiment, when the numbers of 9 bits are added, itis not necessary to wait until the carry output propagates from thefirst bit to the ninth bit gradually. Then, the carry output c₂₃ to thefourth bit and carry output c₂₆ to the seventh bit are added altogetherduring the next third cycle. Accordingly, assuming that T represents thecalculation time of the 1-bit full adder, then the calculation timerequired by the accumulator of this embodiment to add data of 9 bits isequal to calculation times 3T of the 3-bit adders 204A to 204C.Therefore, according to this embodiment, there is the substantialadvantage that the calculation time can be reduced to 5/8 as comparedwith the example of FIG. 4. Further, as the circuits necessary foraccumulation itself in this embodiment, only the registers 205A and 205Bare additionally provided as compared with the example of FIG. 4. Thereis then the advantage that the circuit scale of this embodiment is madenot so large.

During the third cycle, in response to the clock pulse φ1 excited, thesum outputs (s₂₈. . . s₂₀) and the carry outputs c₂₃ and c₂₆ are fedthrough the delay registers 203₀ to 203₈ and 205A and 205B back to theinput sides of the 3-bit adders 204A to 204C and simultaneously numbersx₃ (x₃₈. . . x₃₀) of the third cycle are supplied to the input sides ofthese 3-bit adders 204A to 204C, thereby generating sum outputs (s₃₈. .. S₃₀), a carry output c₃₃ to the fourth bit and a carry output c₃₆ tothe seventh bit as shown in FIG. 11C. Similarly, during the fourthcycle, sum outputs (s₄₈. . . s₄₀) and carry outputs c₄₃ and c₄₆ areobtained as shown in FIG. 11D, and during an n'th cycle, outputs (s_(n)8. . . s_(n) 0) and c_(n) 3 and c_(n) 6 are obtained as sum outputs ofthe 3-bit adders 104A to 204C, a carry output to the fourth bit and acarry output to the seventh bit, respectively.

These sum outputs and carry outputs are redundant expressions ofaccumulated results of the numbers x₁ to x_(n) of n number and can beemployed in actual practice without modification. However, in order tofacilitate the succeeding processing, according to this embodiment, suchredundant expressions are converted into the expressions of ordinary 9bits. More specifically, the clock pulse φ2 is generated at thecompletion of the addition of n cycles thereby to hold the sum outputs(s_(n) 8. . . s_(n) 0) and the carry outputs c_(n) 3 and c_(n) 6 in thedata holding registers 206₀ to 206₈ and 207A and 207B. Then, the sumoutputs and the carry outputs are added as shown in FIG. 11E, therebyobtaining the sum s (s₈. . . s₁, s₀) of 9 bits as the accumulated resultof the ordinary expression. In that case, the addition of the leastsignificant 3 bits is executed by outputting the least significant 3bits (s_(n) 2, s_(n) 1, s_(n) 0) of the sum outputs (s_(n) 8. . . s_(n)0) directly, whereas the addition of the most significant 6 bits isexecuted by the 6-bit adder 208.

As described above, according to this embodiment, since the accumulatedresult of the redundant expression is returned to the ordinaryexpression, the succeeding processing can be made with ease.

The accumulator in the example of FIG. 10 is generalized as shown inFIG. 12, and this type of accumulator will be described with referenceto FIG. 12.

In FIG. 12, reference numerals 209₀ to 209_(p-1) designate r-bit adders(p and r are integers larger than 2), 203₀ to 203_(p) r-1, 205 to205_(p-2) designate delay registers, 206₀ to 206_(p) r-1 and 207 to207_(p-2) designate data holding registers and 210 designates a pr-bitadder. The aforenoted respective circuits are connected similarly tothose of the example of FIG. 10.

According to the example shown in FIG. 12, sums s (s_(p) r-1. . . s₁,s₀) of pr bits are obtained by accumulating numbers x (x_(p) r-1 . . .x₁, x₀) of less than pr bits. In that case, the sums s are expressed asredundant by the sum outputs of the r-bit adders 209₀ to 209_(p-1) andthe carry outputs. In the example of FIG. 12, the addition of the prbits is executed at r bits each. If the accumulated result, for example,is obtained in the form of sums of (pr±1) bits, any one of these r-bitadders 209₀ to 209_(p-1) may be replaced with an adder of (r±1) bits.

Further, since a calculation time required by the accumulator of theexample of FIG. 12 to add the pr bits one time is substantially equal toindividual calculation times rT of the r-bit adders 209₀ to 209_(p-1),there is then the advantage that calculation times necessary for variouspurposes can be obtained by adjusting the value of r.

Furthermore, although the addition of a (p-1) r-bit adder 210 needs acalculation time of (p-1) rT, it is to be appreciated that the totalcalculation time is hardly affected by the calculation time in the (p-1)r-bit adder 210 because only one addition in the (p-1) r-bit adder 210is performed after n (n>>1) accumulations are executed.

Having described preferred embodiments of the invention with referenceto the accompanying drawings, it is to be understood that the inventionis not limited to those precise embodiments and that various changes andmodifications thereof could be effected by one skilled in the artwithout departing from the spirit or scope of the novel concepts of theinvention as defined in the appended claims.

We claim as our invention:
 1. A digital adder circuit for adding binarynumbers, said circuit comprising:at least three adders for adding binarynumbers each composed of a plurality of bits ordered from a leastsignificant bit to a most significant bit, said plurality of bits beingdivided into at least three groups and said adders being respectivelyresponsive to said groups and respectively producing interim addedresults ordered from least significant interim added results tonext-to-least significant interim added results to most significantinterim added results: a first carry calculator responsive to carry datafrom the least significant interim added results and to thenext-to-least significant interim added results for calculating carrydata, a second carry calculator responsive to the carry data of thefirst carry calculator and to the most significant interim added resultsfor producing carry data; a first carry corrector for adding said carrydata from the least significant interim added results to thenext-to-least significant interim added results; and a second carrycorrector for adding said carry data from the first carry calculator tothe most significant interim added results, whereby a sum is generatedhaving no redundancy.
 2. The digital adder circuit according to claim 1wherein at least one of said carry correctors comprises at least one ANDcircuit and at least one exclusive-OR circuit connected thereto.
 3. Anaccumulator for accumulating a plurality of binary numbers sequentiallysupplied thereto, said accumulator comprising:at least three adders of aplurality of bits each, each of said adders producing outputs and carryoutputs; a plurality of registers connected to said adders for delayingsaid outputs and said carry outputs by a determined time, said adderssequentially adding binary numbers sequentially supplied thereto anddelayed outputs of said delay registers to produce redundant accumulatedresults; first and second pluralities of data holding registersconnected to said adders, and an additional adder connected to saidsecond plurality of data holding registers and supplied with saidredundant accumulated results for correcting each of said outputs bysaid carry outputs, said additional adder and said first plurality ofdata holding registers generating an accumulated added result having noredundancy.